1. Technical Field
The invention relates generally to integrated circuits, and more specifically, to programmable dividers for integrated circuits.
2. Background Art
In Phase-Locked Loop (PLL) circuits and similar circuits used for frequency-synthesis applications, divider circuits are used to divide the input signals to achieve a desired output frequency. In order to provide a divider circuit, a binary counter is traditionally used to implement the divide ratio of the divider. Examples of dividers using binary counters are disclosed in the following U.S. Patents: U.S. Pat. No. 4,951,303, issued in August 1990; U.S. Pat. No. 5,111,488, issued in May 1992; U.S. Pat. No. 5,646,564, issued in July 1997; and U.S. Pat. No. 5,491,442, issued in February 1996. Although binary counters effectively divide the input clocks in the aforementioned patents, binary counters may require a relatively large amount of space, especially for a wide range of divide options. Furthermore, increasing the range of desired output frequencies for a conventional divider circuit could substantially increase the amount of space for the divider circuit, depending upon the divide ratio bits used for the binary counter.